1. Field of the Invention
The present invention relates generally to packaging structures and methods for fabricating the same, and more particularly, to a packaging structure with a semiconductor element precisely embedded therein and a method for fabricating the same.
2. Description of Related Art
Besides conventional wiring bonding and flip chip semiconductor packaging technologies, the electronic industry has developed different types of packages, for example, a package having a semiconductor IC chip embedded and electrically connected to a packaging substrate. Such a package has reduced size and improved electrical performance and therefore has become increasing popular.
FIGS. 1A to 1C′ are cross-sectional views showing a conventional packaging structure having an embedded semiconductor element and a method for fabricating the same, wherein FIG. 1B′ shows another embodiment of FIG. 1B, and FIG. 1C′ shows the structure of FIG. 1B′ after performing a sequence of subsequent processes thereon.
Referring to FIG. 1A, a substrate 10 is provided, which has a first surface 10a and an opposite second surface 10b and a predefined opening region 100 for embedding a semiconductor chip. The substrate 10 further has a plurality of conductive through holes 12 penetrating the first surface 10a and the second surface 10b. 
Referring to FIG. 1B, a opening 100′ is formed at the position of the predefined opening region 100 by laser ablation and penetrates the first surface 10a and the second surface 10b. 
However, since the opening 100′ is generally formed through continuous laser ablation, it can easily lead to an uneven surface of the opening 100′ and makes it difficult to provide an accurate shape for the opening 100′. As such, the shape of the opening 100′ deviates from the predefined opening region 100, which adversely affects precise positioning of the semiconductor chip in the opening 100′.
To overcome the drawback, referring to FIG. 1B′, another predefined opening region 101 with larger size is provided and laser ablated so as to form a opening 101′ penetrating the first surface 10a and the second surface 10b. 
Further Referring to FIG. 1C′, a semiconductor chip 13 is disposed in the opening 101′. The semiconductor chip 13 has an active surface 13a with a plurality of electrode pads 131 and an opposite inactive surface 13b, and the active surface 13a is exposed from the opening 100′. Further, a first dielectric layer 14 is formed in the gap between the opening 101′ and the semiconductor chip 13, on the semiconductor chip 13, the first surface 10a and the second surface 10b. Then, a first wiring layer 141 is formed on the first dielectric layers 14 on the first surface 10a, and a plurality of first conductive vias 142 is formed in the first dielectric layer 14 to electrically connect the first wiring layer 141, the conductive through holes 12 and the electrode pads 131. Further, a second wiring layer 171 is formed on the first dielectric layers 14 on the second surface 10b, and a plurality of second conductive vias 172 are formed in the first dielectric layer 14 to electrically connect the second wiring layer 171 and the conductive through holes 12. Thereafter, a first built-up structure 15 is formed on the first dielectric layer 14 and the first wiring layer 141 of the first surface 10a, and a second built-up structure 18 is formed on the first dielectric layer 14 and the second wiring layer 171 of the second surface 10b. 
However, the predefined opening region 101 with a larger size results in a large gap between the semiconductor chip 13 and the opening 101′ and makes it quite difficult to fill the large gap with the first dielectric layer 14. Therefore, recesses can easily be formed on the surface of the first dielectric layer 14, and even short circuit or delamination may occur to the built-up wiring layers, thus decreasing reliability and yield of the entire structure.
Further, the semiconductor chip 13 can be secured in the opening by an adhesive material (not shown). However, the large gap needs a great amount of the adhesive material and the adhesive material is quite expensive, thereby complicating the process and increasing the fabrication cost.
Therefore, it is imperative to provide a packaging structure having an embedded semiconductor element and a method for fabricating the same so as to overcome the above drawbacks.